Mask ROMs (MROMs) are widely used memory devices capable of storing permanently information. MROMs are a kind of non-volatile memory device in which stored information is not erased even if the applied electric power is removed. MROMs are mainly classified into NOR type MROMs and NAND type MROMs as defined by the circuit structure of the memory cell which is used in the device.
MROMs in which data ordered by client is written by use of a mask in a fabrication process have several advantages. First, MROMs have a simplex circuit construction in which no separate data writing circuit is required. Second, MROMs require only a simplex fabrication in which used memory cell structure requires no specific fabrication process. Third, MROMs are capable of providing various memory cell systems from which an appropriate one can be selected according to the use intended.
A widely used method for writing data into MROMs is an ion implantation method. This method performs writing of information for MROMs by use of ion implantation. FIGS. 1A and 1B are schematic and pictorial views respectively illustrating a memory cell array 1 in a typical MROM of the ion implantation type. FIG. 1A is a plan view of a layout of the memory cell array 1. FIG. 1B is a circuit diagram illustrating an equivalent circuit of the memory cell array 1.
In FIG. 1A, a region 2 surrounded by the dotted line represents one of a plurality of memory cells arranged in matrix manner in the memory cell array 1. Each memory cell 2 is realized by either an N type or a P type MOS transistor.
The MROM shown in FIG. 1A is of the ion implantation type, in which a region 8 surrounded by the dashed line corresponds to an impurity-implanted region formed at a channel region of a MOS transistor.
In this case, the memory cell array 1 includes the MOS transistors which each has an impurity-implanted region 8 and others which each has no impurity-implanted region 8. The MOS transistors having the impurity-implanted region 8 become transistors operating in the depletion mode corresponding to the level "1" of information. Opposite, the MOS transistors having no impurity-implanted region 8 become transistors operating in the enhancement mode corresponding to the level "0" of information.
In an MROM of the ion implantation type, the process of implanting ROM code ions must be performed after an order from client. Therefore, there is a turn around time in the fabrication of an MROM when manufacturer takes to fabricate the MROM after an order from client. Early, the process of implanting ROM code ions is performed after the formation of MOS transistors. Afterward, the successive processes are performed to complete the MROM. This results in a low productivity due to very long turn around time.
To date, a post-passivation MROM programming method, in which the process of implanting ROM code ions is performed after the formation of passivation layer, is widely applied. The improved method significantly reduces the turn around time when fabricating an MROM. However, in the method, a high current implanter is required to implant ROM code ions into semiconductor substrate through a thickness of more than 10,000 .ANG.. It is evident that the cost of fabricating MROMs increases due to the requirement of expensive equipment. Besides, the ROM code ions with high energy (more than 500 keV) probably introduces deleterious effects into ROM devices.
U.S. Pat. No. 5,350,703 provides a method for fabricating an MROM device first by etching back partially an array of passivated MOS transistors to expose selected gate electrodes and then by implanting ROM code ions into the employed substrate to complete the information storage of ROM. However, in practical application, the fabrication method (etching back method) is difficult for manufacturers to control the etching stop point without excessive etching back. So the etching back method would cause the damage of selected transistors.
Accordingly, an objective of the invention is to fabricate post-passivation MROMs via a medium current implanter. By use of a medium current implanter, the invention reduces the cost and deleterious effects for fabricating post-passivation MROMs.
Another objective of the invention is to employ an etching back method to directly form a ROM code pattern on an array of passivated MOS transistors without the damage of selected transistors.